[mpeg2] Clue on VIA chipset problem

[Richard Hodges <rh@matriplex.com>]

To Frank, Paul, and anyone else with the "VIA chipset problem":

I have also seen this, and just now worked around it.  Maybe
you can take my workaround and find out what is really going on.

Since the Altera 6000 is behind the PLX, I figure that the motherboard
really should not be able to influence the communication between these
parts.  So any difference between my board that works (Intel) and the new
one (KT7A/VIA) should be the way the data is sent across the PCI bus.

What could it be?  My best guess is that the VIA chipset delays the PCI
transactions, which causes the Altera bit clocking to have incorrect
values.

Although the 6000 specifies 10ns data setup, 30ns clock high, and 30ns
clock low (16 mhz), I have noticed that the data will not be stable if you
clock it that fast.  This is probably due to capacitance on the data and
clock lines dampening the signals.  For my Intel board, my clock was 1uS
high and 1uS low.  This would not initialize the Altera 6k on my VIA
board, but doubling the delay seems to be enough.  I also doubled the 5
microsecond delay after the nCONFIG low-high edge and the 5 uS delay
waiting for user mode after programming.

Blindly changing values to see what works is not a solution.  But 
hopefully you can find this information helpful in tracking down
the real problem - which I think must be in the PCI transactions.

All the best,

-Richard

-------------------------------------------
   Richard Hodges   | Matriplex, inc.
   Product Manager  | 769 Basque Way
  rh@matriplex.com  | Carson City, NV 89706
    775-886-6477    | www.matriplex.com