[linux-dvb] HowTo for new tuner

Manu Abraham abraham.manu at gmail.com
Thu Aug 2 14:11:55 CEST 2007


On 8/2/07, MikeW <mw_phil at yahoo.co.uk> wrote:
> I have explored the 2.6.19.1 drivers source and checked out
> LinuxTv.org, plus plenty of other searching,
> in the hope of finding a step-by-step/HowTo guide or documentation
> for adding/implementing a new frontend tuner device, but in vain.
>
> Can anyone recommend a link ?


What kind of a tuner are you looking at ? Or better, which tuner is it ?


> Additionally what is the best way to represent a tuner that has several
> frequency bands - the dvb_tuner_info and dvb_tuner_ops structs don't
> appear to be able to deal with this easily.

I have a tuner over here, which supports multiple bands. What i do is
like this for ex (in my tuning function):



	/* RF tuning function */
	if (rf_lof < 40000000)
		return -1;

	reg1 = mxl500x_cwread_change(state, MXL500x_DC1);
	reg2 = mxl500x_cwread_change(state, MXL500x_DC2);
	reg3 = mxl500x_cwread_change(state, MXL500x_DC3);
	reg4 = mxl500x_cwread_change(state, MXL500x_DC4);
 	if ((rf_lof >= 40000000) && (rf_lof <= 75000000)) {

		MXL500x_SETFIELD(DC1_DN_POLY, reg1, 2);
		MXL500x_SETFIELD(DC1_DN_CAP_RFLPF_1, reg1,
(MXL500x_LSB(DC1_DN_CAP_RFLPF_1, 423)));
		MXL500x_SETFIELD(DC2_DN_CAP_RFLPF_0, reg2,
(MXL500x_MSB(DC2_DN_CAP_RFLPF_0, 423)));
		MXL500x_SETFIELD(DC3_DN_RFGAIN, reg3, 3);
		MXL500x_SETFIELD(DC3_DN_EN_VHFUHFBAR, reg3, 1);
		MXL500x_SETFIELD(DC4_DN_GAIN_ADJUST, reg4, 1);
	}
	if ((rf_lof >   75000000) && (rf_lof <= 100000000)) {

		MXL500x_SETFIELD(DC1_DN_POLY, reg1, 3);
		MXL500x_SETFIELD(DC1_DN_CAP_RFLPF_1, reg1,
(MXL500x_LSB(DC1_DN_CAP_RFLPF_1, 222)));
		MXL500x_SETFIELD(DC2_DN_CAP_RFLPF_0, reg2,
(MXL500x_MSB(DC2_DN_CAP_RFLPF_0, 222)));
		MXL500x_SETFIELD(DC3_DN_RFGAIN, reg3, 3);
		MXL500x_SETFIELD(DC3_DN_EN_VHFUHFBAR, reg3, 1);
		MXL500x_SETFIELD(DC4_DN_GAIN_ADJUST, reg4, 1);
	}
	if ((rf_lof >  100000000) && (rf_lof <= 150000000)) {

		MXL500x_SETFIELD(DC1_DN_POLY, reg1, 3);
		MXL500x_SETFIELD(DC1_DN_CAP_RFLPF_1, reg1,
(MXL500x_LSB(DC1_DN_CAP_RFLPF_1, 147)));
		MXL500x_SETFIELD(DC2_DN_CAP_RFLPF_0, reg2,
(MXL500x_MSB(DC2_DN_CAP_RFLPF_0, 147)));
		MXL500x_SETFIELD(DC3_DN_RFGAIN, reg3, 3);
		MXL500x_SETFIELD(DC3_DN_EN_VHFUHFBAR, reg3, 1);
		MXL500x_SETFIELD(DC4_DN_GAIN_ADJUST, reg4, 2);

	}
....... .....

	if ((rf_lof >  680000000) && (rf_lof <= 900000000)) {

		MXL500x_SETFIELD(RFSYN6_RFSYN_EN_OUTMUX, reg6, 0);
		MXL500x_SETFIELD(RFSYN6_RFSYN_SEL_VCO_OUT, reg6, 1);
		MXL500x_SETFIELD(RFSYN6_RFSYN_SEL_VCO_HI, reg6, 1);
		MXL500x_SETFIELD(RFSYN6_RFSYN_SEL_DIVM, reg6, 1);
		MXL500x_SETFIELD(RFSYN5_RFSYN_RF_DIV_BIAS, reg5, 1);
		MXL500x_SETFIELD(DC2_DN_SEL_FREQ, reg2, 0);
		f_min = 680000000, f_max = 900000000;
		div = 4;
	}
	mxl500x_cwrite_change(state, MXL500x_RFSYN6, reg6);
	mxl500x_cwrite_change(state, MXL500x_RFSYN5, reg5);
	mxl500x_cwrite_change(state, MXL500x_DC2, reg2);

	/* equation 3 */
	reg5 = mxl500x_cwread_change(state, MXL500x_RFSYN5);
	eq3 = (((f_max - rf_lof) / 1000) * 32) / ((f_max - f_min) / 1000) + 8;
	MXL500x_SETFIELD(RFSYN5_RFSYN_VCO_BIAS, reg5, eq3);
	mxl500x_cwrite_change(state, MXL500x_RFSYN5, reg5);



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