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2015-10-05T01:31:04Z
User contributions
MediaWiki 1.22.15
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-03-16T23:07:40Z
<p>Merbanan: /* Lock 88473 */ wrong specs</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is not set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
==== DVB-T2 ====<br />
* Read register 0x8A in T2 bank as value<br />
* Or value with 0x20 then and with 0xef as value<br />
* Write register 0x8A in T2 bank from value<br />
* Read register 0xC0 in T2 bank (upper)<br />
* Read register 0xC1 in T2 bank (middle)<br />
* Read register 0xC2 in T2 bank (lower)<br />
* Or together as error<br />
* Read register 0x8B in T2 bank as berlen<br />
* Write register 0xC5 in T2 bank with 0x3<br />
* If berlen bit 0 is set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 32400, 38880, 43200, 48600, 51840, 54000<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* If berlen bit 0 is not set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 28800, 38880, 43200, 47520, 50400, 53280<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
==== Error Free ====<br />
* Read register 0xC3 in T2 bank as value<br />
* Invert only bit 0 in value and return the result of the inversion<br />
<br />
==== Guard Interval ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 4 to 6 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
4, 1/128<br />
5, 19/128<br />
6, 19/256<br />
7, Unknown (not defined)<br />
<br />
==== Selected PLP ====<br />
* Read register 0x32 in T2 bank<br />
* Return result<br />
<br />
==== Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC6 in T2 bank<br />
* Bit 0 to 7 forms an index to the following table<br />
0, TS<br />
1, GS<br />
2, TS and GS<br />
*, Unknown (not defined)<br />
<br />
==== Bandwidth Ext ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Return the value of bit 7<br />
<br />
==== FFT Mode ====<br />
* Read register 0x93 in T2 bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1k<br />
1, 2k<br />
2, 4k<br />
3, 8k<br />
4, 16k<br />
5, 32k<br />
<br />
==== S1 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 4 to 6 forms a value s1<br />
<br />
==== S2 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 0 to 3 forms a value s2<br />
<br />
==== PAPR ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 0 to 4 forms an index to the following table<br />
0, No PAPR<br />
1, ACE-PAPR<br />
2, TR-PAPR<br />
3, ACE and PAPR<br />
*, Unknown (not defined)<br />
<br />
==== L1 Modulation ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 4 to 7 forms an index to the following table<br />
0, BPSK<br />
1, QPSK<br />
2, 16QAM<br />
3, 64QAM<br />
*, Unknown (not defined)<br />
<br />
==== L1 Code Rate ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/2<br />
1, 3/5<br />
2, 2/3<br />
3, 3/4<br />
<br />
==== L1 Fec Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 0 and 1 forms a value as fec_type<br />
<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-22T23:05:02Z
<p>Merbanan: /* DVB-T2 Signal Properties */</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
==== DVB-T2 ====<br />
* Read register 0x8A in T2 bank as value<br />
* Or value with 0x20 then and with 0xef as value<br />
* Write register 0x8A in T2 bank from value<br />
* Read register 0xC0 in T2 bank (upper)<br />
* Read register 0xC1 in T2 bank (middle)<br />
* Read register 0xC2 in T2 bank (lower)<br />
* Or together as error<br />
* Read register 0x8B in T2 bank as berlen<br />
* Write register 0xC5 in T2 bank with 0x3<br />
* If berlen bit 0 is set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 32400, 38880, 43200, 48600, 51840, 54000<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* If berlen bit 0 is not set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 28800, 38880, 43200, 47520, 50400, 53280<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
==== Error Free ====<br />
* Read register 0xC3 in T2 bank as value<br />
* Invert only bit 0 in value and return the result of the inversion<br />
<br />
==== Guard Interval ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 4 to 6 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
4, 1/128<br />
5, 19/128<br />
6, 19/256<br />
7, Unknown (not defined)<br />
<br />
==== Selected PLP ====<br />
* Read register 0x32 in T2 bank<br />
* Return result<br />
<br />
==== Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC6 in T2 bank<br />
* Bit 0 to 7 forms an index to the following table<br />
0, TS<br />
1, GS<br />
2, TS and GS<br />
*, Unknown (not defined)<br />
<br />
==== Bandwidth Ext ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Return the value of bit 7<br />
<br />
==== FFT Mode ====<br />
* Read register 0x93 in T2 bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1k<br />
1, 2k<br />
2, 4k<br />
3, 8k<br />
4, 16k<br />
5, 32k<br />
<br />
==== S1 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 4 to 6 forms a value s1<br />
<br />
==== S2 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 0 to 3 forms a value s2<br />
<br />
==== PAPR ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 0 to 4 forms an index to the following table<br />
0, No PAPR<br />
1, ACE-PAPR<br />
2, TR-PAPR<br />
3, ACE and PAPR<br />
*, Unknown (not defined)<br />
<br />
==== L1 Modulation ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 4 to 7 forms an index to the following table<br />
0, BPSK<br />
1, QPSK<br />
2, 16QAM<br />
3, 64QAM<br />
*, Unknown (not defined)<br />
<br />
==== L1 Code Rate ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/2<br />
1, 3/5<br />
2, 2/3<br />
3, 3/4<br />
<br />
==== L1 Fec Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 0 and 1 forms a value as fec_type<br />
<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-22T00:13:52Z
<p>Merbanan: /* DVB-T2 Signal Properties */</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
==== DVB-T2 ====<br />
* Read register 0x8A in T2 bank as value<br />
* Or value with 0x20 then and with 0xef as value<br />
* Write register 0x8A in T2 bank from value<br />
* Read register 0xC0 in T2 bank (upper)<br />
* Read register 0xC1 in T2 bank (middle)<br />
* Read register 0xC2 in T2 bank (lower)<br />
* Or together as error<br />
* Read register 0x8B in T2 bank as berlen<br />
* Write register 0xC5 in T2 bank with 0x3<br />
* If berlen bit 0 is set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 32400, 38880, 43200, 48600, 51840, 54000<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* If berlen bit 0 is not set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 28800, 38880, 43200, 47520, 50400, 53280<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
==== Error Free ====<br />
* Read register 0xC3 in T2 bank as value<br />
* Invert only bit 0 in value and return the result of the inversion<br />
<br />
==== Guard Interval ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 4 to 6 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
4, 1/128<br />
5, 19/128<br />
6, 19/256<br />
7, Unknown (not defined)<br />
<br />
==== Selected PLP ====<br />
* Read register 0x32 in T2 bank<br />
* Return result<br />
<br />
==== Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC6 in T2 bank<br />
* Bit 0 to 7 forms an index to the following table<br />
0, TS<br />
1, GS<br />
2, TS and GS<br />
*, Unknown (not defined)<br />
<br />
==== Bandwidth Ext ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Return the value of bit 7<br />
<br />
==== FFT Mode ====<br />
* Read register 0x93 in T2 bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1k<br />
1, 2k<br />
2, 4k<br />
3, 8k<br />
4, 16k<br />
5, 32k<br />
<br />
==== S1 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 4 to 6 forms a value s1<br />
<br />
==== S2 ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Bit 0 to 3 forms a value s2<br />
<br />
==== PAPR ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 0 to 3 forms a value papr<br />
<br />
==== PAPR ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 0 to 4 forms an index to the following table<br />
0, No PAPR<br />
1, ACE-PAPR<br />
2, TR-PAPR<br />
3, ACE and PAPR<br />
*, Unknown (not defined)<br />
<br />
==== L1 Modulation ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 4 to 7 forms an index to the following table<br />
...<br />
<br />
==== L1 Code Rate ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC9 in T2 bank<br />
* Bit 2 and 3 forms an index to the following table<br />
...<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-21T21:44:53Z
<p>Merbanan: /* Statistics */ add moar dvb-t2 parameters</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
==== DVB-T2 ====<br />
* Read register 0x8A in T2 bank as value<br />
* Or value with 0x20 then and with 0xef as value<br />
* Write register 0x8A in T2 bank from value<br />
* Read register 0xC0 in T2 bank (upper)<br />
* Read register 0xC1 in T2 bank (middle)<br />
* Read register 0xC2 in T2 bank (lower)<br />
* Or together as error<br />
* Read register 0x8B in T2 bank as berlen<br />
* Write register 0xC5 in T2 bank with 0x3<br />
* If berlen bit 0 is set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 32400, 38880, 43200, 48600, 51840, 54000<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* If berlen bit 0 is not set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 28800, 38880, 43200, 47520, 50400, 53280<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
==== Error Free ====<br />
* Read register 0xC3 in T2 bank as value<br />
* Invert only bit 0 in value and return the result of the inversion<br />
<br />
==== Guard Interval ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC8 in T2 bank<br />
* Bit 4 to 6 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
4, 1/128<br />
5, 19/128<br />
6, 19/256<br />
7, Unknown (not defined)<br />
<br />
==== Selected PLP ====<br />
* Read register 0x32 in T2 bank<br />
* Return result<br />
<br />
==== Type ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC6 in T2 bank<br />
* Bit 0 to 7 forms an index to the following table<br />
0, TS<br />
1, GS<br />
2, TS and GS<br />
*, Unknown (not defined)<br />
<br />
==== Bandwidth Ext ====<br />
* Write 0x0 to register 0xC4 in T2 bank<br />
* Write 0x0 to register 0xC5 in T2 bank<br />
* Read register 0xC7 in T2 bank<br />
* Return the value of bit 7<br />
<br />
==== FFT Mode ====<br />
* Read register 0x93 in T2 bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1k<br />
1, 2k<br />
2, 4k<br />
3, 8k<br />
4, 16k<br />
5, 32k<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-21T20:10:01Z
<p>Merbanan: /* BER (Bit Error Rate) */ dvb-t2 ber</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
==== DVB-T2 ====<br />
* Read register 0x8A in T2 bank as value<br />
* Or value with 0x20 then and with 0xef as value<br />
* Write register 0x8A in T2 bank from value<br />
* Read register 0xC0 in T2 bank (upper)<br />
* Read register 0xC1 in T2 bank (middle)<br />
* Read register 0xC2 in T2 bank (lower)<br />
* Or together as error<br />
* Read register 0x8B in T2 bank as berlen<br />
* Write register 0xC5 in T2 bank with 0x3<br />
* If berlen bit 0 is set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 32400, 38880, 43200, 48600, 51840, 54000<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* If berlen bit 0 is not set (fec_type)<br />
** Bit 2 to 4 in berlen forms an index into the following table, take value as fec_type_m<br />
** 28800, 38880, 43200, 47520, 50400, 53280<br />
** Take berlen low nibble shifted up 1 time multiplied with fec_type_m as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-21T00:05:31Z
<p>Merbanan: /* Statistics */ BER for dvb-c and dvb-t</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== BER (Bit Error Rate) ===<br />
==== DVB-T/C ====<br />
* Read register 0x78 in T bank as value<br />
* And value with 0xDF<br />
* Write register 0x78 in T bank from value<br />
* Read register 0x7D in T bank as value<br />
* And value with 0xF0 and then or with 0x5<br />
* Write register 0x7D in T bank from value<br />
* Read register 0x9F in T bank (upper)<br />
* Read register 0xA0 in T bank (middle)<br />
* Read register 0xA1 in T bank (lower)<br />
* Or together as error<br />
* Read register 0xA2 in T bank (upper)<br />
* Read register 0xA3 in T bank (lower)<br />
* Or together as value<br />
* Take value and multiply with 8 and 203 as sum<br />
* Take sum divided by error as ber<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-20T23:24:25Z
<p>Merbanan: /* Statistics */ Add CNR</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== CNR (Carrier Noise Ratio) ===<br />
==== DVB-T ====<br />
* Read register 0x9C in T bank (upper)<br />
* Read register 0x9D in T bank (lower)<br />
* Or both values as value<br />
* if value is 0 then cnr is 0<br />
* calculate 10log of 65536 divided by value and then add 200 as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-T2 ====<br />
* Read register 0xBD in T2 bank (upper)<br />
* Read register 0xBE in T2 bank (lower)<br />
* Or both registers as value<br />
* If value is 0 cnr is 0<br />
* Read register 0xBC in T2 bank as flag<br />
* If bit 2 in flag is set (MISO)<br />
** calculate 10log of 16384 divided by value and then subtract 600 as result<br />
** if result is less then 0 cnr is 0<br />
* If bit 2 in flag is not set (SISO)<br />
** calculate 10log of 65536 divided by value and then add 200 as result<br />
** if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
==== DVB-C ====<br />
* Read register 0xA1 in C bank (upper)<br />
* Read register 0xA2 in C bank (lower)<br />
* Or both registers as carrier<br />
* Read register 0xA3 in C bank (upper)<br />
* Read register 0xA4 in C bank (lower)<br />
* Or both registers as noise<br />
* if noise is 0 cnr is 0<br />
* calculate 10log of signal multiplied by 8 and divided by noise as result<br />
* if result is less then 0 cnr is 0<br />
* take result divided by 100 as cnr<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
=== DVB-T2 Signal Properties ===<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-19T23:14:08Z
<p>Merbanan: /* Statistics */</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
==== FEC High Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 3 and 5 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== FEC Low Priority Code Rate ====<br />
* Read register 0x8A in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, 1/2<br />
1, 2/3<br />
2, 3/4<br />
3, 5/6<br />
4, 7/8<br />
5, Unknown (not defined)<br />
<br />
==== Cell ID ====<br />
* Read register 0x90 (upper) in T bank<br />
* Read register 0x91 (lower) in T bank<br />
* Return both values ored together<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-19T23:02:24Z
<p>Merbanan: /* Statistics */ Add moar</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
=== DVB-T Signal Properties ===<br />
<br />
==== TPS length indicator ====<br />
* Read register 0x88 in T bank<br />
* Bit 0 to 6 forms a length value<br />
<br />
<br />
==== Hierarchy ====<br />
* Read register 0x89 in T bank<br />
* Bit 0 to 2 forms an index to the following table<br />
0, No heirarchy<br />
1, alpha=1<br />
2, alpha=2<br />
3, alpha=4<br />
4, Unknown (not defined)<br />
5, Unknown (not defined)<br />
6, Unknown (not defined)<br />
7, Unknown (not defined)<br />
<br />
==== Constellation ====<br />
* Read register 0x89 in T bank<br />
* Bit 3 and 4 forms an index to the following table<br />
0, QPSK<br />
1, 16QAM<br />
2, 64QAM<br />
3, Unknown (not defined)<br />
<br />
<br />
<br />
<br />
==== FFT Mode ====<br />
* Read register 0x8B in T bank<br />
* Bit 0 and 1 forms an index to the following table<br />
0, 2k<br />
1, 8k<br />
2, 4k<br />
3, Unknown (not defined)<br />
<br />
==== Guard Interval ====<br />
* Read register 0x8B in T bank<br />
* Bit 2 and 3 forms an index to the following table<br />
0, 1/32<br />
1, 1/16<br />
2, 1/8<br />
3, 1/4<br />
<br />
<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-18T23:17:22Z
<p>Merbanan: Add per and firmware version</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
=== Firmware version ===<br />
* Read register 0xF1 in T bank<br />
* The returned value is the firmware version<br />
<br />
=== PER ===<br />
* Read register 0xE1 in T bank (upper)<br />
* Read register 0xE2 in T bank (lower)<br />
* Or both values as error<br />
* Read register 0xE3 in T bank (upper)<br />
* Read register 0xE4 in T bank (lower)<br />
* Or both values as per_len<br />
* Return error * 100 / per_len<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-18T01:06:20Z
<p>Merbanan: Add signal strength</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
== Statistics ==<br />
=== Signal strength ===<br />
* Read register 0x8E (upper agc reg) in T2 bank<br />
* Read register 0x8F (lower agc reg) in T2 bank<br />
* Return both values ored together<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2015-01-13T22:41:06Z
<p>Merbanan: Add lock logic for 88473 revision</p>
<hr />
<div>=== MN88472 ===<br />
<br />
The MN88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Lock 88473 ===<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x85 in C1 bank<br />
* If bit 6 is set then read register 0x89 in C1 bank<br />
* If bit 1 is set then we have lock.<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x62 in T1 bank.<br />
* If bit 5 and 7 is set then<br />
* If the low nibble in the result is >8 there is a lock<br />
* If the low nibble in the result is >2 there is a signal<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x8B in T2 bank.<br />
* If bit 6 is set then<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2014-11-15T23:32:37Z
<p>Merbanan: Add 1.7MHz</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 1.7MHz ====<br />
<br />
{T2,0x10,0x17},<br />
{T2,0x11,0xba},<br />
{T2,0x12,0x11},<br />
{T2,0x13,0xf4},<br />
{T2,0x14,0x6f},<br />
{T2,0x15,0x64},<br />
{T2,0x16,0x1c},<br />
{T2,0x17,0x00},<br />
{T2,0x18,0x1c},<br />
{T2,0x19,0x00},<br />
<br />
<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Astrometa_DVB-T2
Astrometa DVB-T2
2014-03-16T20:55:27Z
<p>Merbanan: /* External ts mode */</p>
<hr />
<div>==RTL2832P configuration==<br />
<br />
The RTL2832P has 2 PID filter paths. One for the internal demod and one for a possible external one.<br />
<br />
=== External ts mode ===<br />
0x21[3] enable_ETS, set to enable external ts input<br />
0x21[5] pass_err, when set reject error packets<br />
0x21[6] PID_mode, when set reject matched PIDs<br />
0x21[7] PID_output, when set output data from enabled PID filters<br />
0x22[7-0] PID_enable, when set enable PID in corresponding register (0-7)<br />
0x23[7-0] PID_enable, when set enable PID in corresponding register (8-15)<br />
0x24[7-0] PID_enable, when set enable PID in corresponding register (16-23)<br />
0x25[7-0] PID_enable, when set enable PID in corresponding register (24-31)<br />
0x26-0x27[12-0] PID_0, PID storage register 13 bits wide<br />
0x28-0x29[12-0] PID_1, PID storage register 13 bits wide<br />
0x2A-0x2B[12-0] PID_2, PID storage register 13 bits wide<br />
0x2C-0x2D[12-0] PID_3, PID storage register 13 bits wide<br />
0x2E-0x2F[12-0] PID_4, PID storage register 13 bits wide<br />
0x30-0x31[12-0] PID_5, PID storage register 13 bits wide<br />
0x32-0x33[12-0] PID_6, PID storage register 13 bits wide<br />
0x34-0x35[12-0] PID_7, PID storage register 13 bits wide<br />
0x36-0x37[12-0] PID_8, PID storage register 13 bits wide<br />
0x38-0x39[12-0] PID_9, PID storage register 13 bits wide<br />
0x3A-0x3B[12-0] PID_10, PID storage register 13 bits wide<br />
0x3C-0x3D[12-0] PID_11, PID storage register 13 bits wide<br />
0x3E-0x3F[12-0] PID_12, PID storage register 13 bits wide<br />
0x40-0x41[12-0] PID_13, PID storage register 13 bits wide<br />
0x42-0x43[12-0] PID_14, PID storage register 13 bits wide<br />
0x44-0x45[12-0] PID_15, PID storage register 13 bits wide<br />
0x46-0x47[12-0] PID_16, PID storage register 13 bits wide<br />
0x48-0x49[12-0] PID_17, PID storage register 13 bits wide<br />
0x4A-0x4B[12-0] PID_18, PID storage register 13 bits wide<br />
0x4C-0x4D[12-0] PID_19, PID storage register 13 bits wide<br />
0x4E-0x4F[12-0] PID_20, PID storage register 13 bits wide<br />
0x50-0x51[12-0] PID_21, PID storage register 13 bits wide<br />
0x52-0x53[12-0] PID_22, PID storage register 13 bits wide<br />
0x54-0x55[12-0] PID_23, PID storage register 13 bits wide<br />
0x56-0x57[12-0] PID_24, PID storage register 13 bits wide<br />
0x58-0x59[12-0] PID_25, PID storage register 13 bits wide<br />
0x5A-0x5B[12-0] PID_26, PID storage register 13 bits wide<br />
0x5C-0x5D[12-0] PID_27, PID storage register 13 bits wide<br />
0x5E-0x5F[12-0] PID_28, PID storage register 13 bits wide<br />
<br />
These filters would overlap with the internal ts address space.<br />
<br />
0x60-0x61[12-0] PID_29, PID storage register 13 bits wide<br />
0x62-0x63[12-0] PID_30, PID storage register 13 bits wide<br />
0x64-0x65[12-0] PID_31, PID storage register 13 bits wide<br />
<br />
Most likely the the external PID filter path has less then 32 pid filters.<br />
<br />
=== Internal ts mode ===<br />
0x61[5] pass_err, when set reject error packets<br />
0x61[6] PID_mode, when set reject matched PIDs<br />
0x61[7] PID_output, when set output data from enabled PID filters<br />
0x62[7-0] PID_enable, when set enable PID in corresponding register (0-7)<br />
0x63[7-0] PID_enable, when set enable PID in corresponding register (8-15)<br />
0x64[7-0] PID_enable, when set enable PID in corresponding register (16-23)<br />
0x65[7-0] PID_enable, when set enable PID in corresponding register (24-31)<br />
0x66-0x67[12-0] PID_0, PID storage register 13 bits wide<br />
0x68-0x69[12-0] PID_1, PID storage register 13 bits wide<br />
0x6A-0x6B[12-0] PID_2, PID storage register 13 bits wide<br />
0x6C-0x6D[12-0] PID_3, PID storage register 13 bits wide<br />
0x6E-0x6F[12-0] PID_4, PID storage register 13 bits wide<br />
0x70-0x71[12-0] PID_5, PID storage register 13 bits wide<br />
0x72-0x73[12-0] PID_6, PID storage register 13 bits wide<br />
0x74-0x75[12-0] PID_7, PID storage register 13 bits wide<br />
0x76-0x77[12-0] PID_8, PID storage register 13 bits wide<br />
0x78-0x79[12-0] PID_9, PID storage register 13 bits wide<br />
0x7A-0x7B[12-0] PID_10, PID storage register 13 bits wide<br />
0x7C-0x7D[12-0] PID_11, PID storage register 13 bits wide<br />
0x7E-0x7F[12-0] PID_12, PID storage register 13 bits wide<br />
0x80-0x81[12-0] PID_13, PID storage register 13 bits wide<br />
0x82-0x83[12-0] PID_14, PID storage register 13 bits wide<br />
0x84-0x85[12-0] PID_15, PID storage register 13 bits wide<br />
0x86-0x87[12-0] PID_16, PID storage register 13 bits wide<br />
0x88-0x89[12-0] PID_17, PID storage register 13 bits wide<br />
0x8A-0x8B[12-0] PID_18, PID storage register 13 bits wide<br />
0x8C-0x8D[12-0] PID_19, PID storage register 13 bits wide<br />
0x8E-0x8F[12-0] PID_20, PID storage register 13 bits wide<br />
0x90-0x91[12-0] PID_21, PID storage register 13 bits wide<br />
0x92-0x93[12-0] PID_22, PID storage register 13 bits wide<br />
0x94-0x95[12-0] PID_23, PID storage register 13 bits wide<br />
0x96-0x97[12-0] PID_24, PID storage register 13 bits wide<br />
0x98-0x99[12-0] PID_25, PID storage register 13 bits wide<br />
0x9A-0x9B[12-0] PID_26, PID storage register 13 bits wide<br />
0x9C-0x9D[12-0] PID_27, PID storage register 13 bits wide<br />
0x9E-0x9F[12-0] PID_28, PID storage register 13 bits wide<br />
0xA0-0xA1[12-0] PID_29, PID storage register 13 bits wide<br />
0xA2-0xA3[12-0] PID_30, PID storage register 13 bits wide<br />
0xA4-0xA5[12-0] PID_31, PID storage register 13 bits wide</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Astrometa_DVB-T2
Astrometa DVB-T2
2014-03-16T20:53:06Z
<p>Merbanan: </p>
<hr />
<div>==RTL2832P configuration==<br />
<br />
The RTL2832P has 2 PID filter paths. One for the internal demod and one for a possible external one.<br />
<br />
=== External ts mode ===<br />
0x21[3] enable_ETS, set to enable external ts input<br />
0x21[5] pass_err, when set reject error packets<br />
0x21[6] PID_mode, when set reject matched PIDs<br />
0x21[7] PID_output, when set output data from enabled PID filters<br />
0x22[7-0] PID_enable, when set enable PID in corresponding register (0-7)<br />
0x23[7-0] PID_enable, when set enable PID in corresponding register (8-15)<br />
0x24[7-0] PID_enable, when set enable PID in corresponding register (16-23)<br />
0x25[7-0] PID_enable, when set enable PID in corresponding register (24-31)<br />
0x26-0x27[12-0] PID_0, PID storage register 13 bits wide<br />
0x28-0x29[12-0] PID_1, PID storage register 13 bits wide<br />
0x2A-0x2B[12-0] PID_2, PID storage register 13 bits wide<br />
0x2C-0x2D[12-0] PID_3, PID storage register 13 bits wide<br />
0x2E-0x2F[12-0] PID_4, PID storage register 13 bits wide<br />
0x30-0x31[12-0] PID_5, PID storage register 13 bits wide<br />
0x32-0x33[12-0] PID_6, PID storage register 13 bits wide<br />
0x34-0x35[12-0] PID_7, PID storage register 13 bits wide<br />
0x36-0x37[12-0] PID_8, PID storage register 13 bits wide<br />
0x38-0x39[12-0] PID_9, PID storage register 13 bits wide<br />
0x3A-0x3B[12-0] PID_10, PID storage register 13 bits wide<br />
0x3C-0x3D[12-0] PID_11, PID storage register 13 bits wide<br />
0x3E-0x3F[12-0] PID_12, PID storage register 13 bits wide<br />
0x40-0x41[12-0] PID_13, PID storage register 13 bits wide<br />
0x42-0x43[12-0] PID_14, PID storage register 13 bits wide<br />
0x44-0x45[12-0] PID_15, PID storage register 13 bits wide<br />
0x46-0x47[12-0] PID_16, PID storage register 13 bits wide<br />
0x48-0x49[12-0] PID_17, PID storage register 13 bits wide<br />
0x4A-0x4B[12-0] PID_18, PID storage register 13 bits wide<br />
0x4C-0x4D[12-0] PID_19, PID storage register 13 bits wide<br />
0x4E-0x4F[12-0] PID_20, PID storage register 13 bits wide<br />
0x50-0x51[12-0] PID_21, PID storage register 13 bits wide<br />
0x52-0x53[12-0] PID_22, PID storage register 13 bits wide<br />
0x54-0x55[12-0] PID_23, PID storage register 13 bits wide<br />
0x56-0x57[12-0] PID_24, PID storage register 13 bits wide<br />
0x58-0x59[12-0] PID_25, PID storage register 13 bits wide<br />
0x5A-0x5B[12-0] PID_26, PID storage register 13 bits wide<br />
0x5C-0x5D[12-0] PID_27, PID storage register 13 bits wide<br />
0x5E-0x5F[12-0] PID_28, PID storage register 13 bits wide<br />
<br />
These filters would overlap with the 0x61 address.<br />
<br />
0x60-0x61[12-0] PID_29, PID storage register 13 bits wide<br />
0x62-0x63[12-0] PID_30, PID storage register 13 bits wide<br />
0x64-0x65[12-0] PID_31, PID storage register 13 bits wide<br />
<br />
Most likely the the external PID filter path has less then 32 pid filters.<br />
<br />
=== Internal ts mode ===<br />
0x61[5] pass_err, when set reject error packets<br />
0x61[6] PID_mode, when set reject matched PIDs<br />
0x61[7] PID_output, when set output data from enabled PID filters<br />
0x62[7-0] PID_enable, when set enable PID in corresponding register (0-7)<br />
0x63[7-0] PID_enable, when set enable PID in corresponding register (8-15)<br />
0x64[7-0] PID_enable, when set enable PID in corresponding register (16-23)<br />
0x65[7-0] PID_enable, when set enable PID in corresponding register (24-31)<br />
0x66-0x67[12-0] PID_0, PID storage register 13 bits wide<br />
0x68-0x69[12-0] PID_1, PID storage register 13 bits wide<br />
0x6A-0x6B[12-0] PID_2, PID storage register 13 bits wide<br />
0x6C-0x6D[12-0] PID_3, PID storage register 13 bits wide<br />
0x6E-0x6F[12-0] PID_4, PID storage register 13 bits wide<br />
0x70-0x71[12-0] PID_5, PID storage register 13 bits wide<br />
0x72-0x73[12-0] PID_6, PID storage register 13 bits wide<br />
0x74-0x75[12-0] PID_7, PID storage register 13 bits wide<br />
0x76-0x77[12-0] PID_8, PID storage register 13 bits wide<br />
0x78-0x79[12-0] PID_9, PID storage register 13 bits wide<br />
0x7A-0x7B[12-0] PID_10, PID storage register 13 bits wide<br />
0x7C-0x7D[12-0] PID_11, PID storage register 13 bits wide<br />
0x7E-0x7F[12-0] PID_12, PID storage register 13 bits wide<br />
0x80-0x81[12-0] PID_13, PID storage register 13 bits wide<br />
0x82-0x83[12-0] PID_14, PID storage register 13 bits wide<br />
0x84-0x85[12-0] PID_15, PID storage register 13 bits wide<br />
0x86-0x87[12-0] PID_16, PID storage register 13 bits wide<br />
0x88-0x89[12-0] PID_17, PID storage register 13 bits wide<br />
0x8A-0x8B[12-0] PID_18, PID storage register 13 bits wide<br />
0x8C-0x8D[12-0] PID_19, PID storage register 13 bits wide<br />
0x8E-0x8F[12-0] PID_20, PID storage register 13 bits wide<br />
0x90-0x91[12-0] PID_21, PID storage register 13 bits wide<br />
0x92-0x93[12-0] PID_22, PID storage register 13 bits wide<br />
0x94-0x95[12-0] PID_23, PID storage register 13 bits wide<br />
0x96-0x97[12-0] PID_24, PID storage register 13 bits wide<br />
0x98-0x99[12-0] PID_25, PID storage register 13 bits wide<br />
0x9A-0x9B[12-0] PID_26, PID storage register 13 bits wide<br />
0x9C-0x9D[12-0] PID_27, PID storage register 13 bits wide<br />
0x9E-0x9F[12-0] PID_28, PID storage register 13 bits wide<br />
0xA0-0xA1[12-0] PID_29, PID storage register 13 bits wide<br />
0xA2-0xA3[12-0] PID_30, PID storage register 13 bits wide<br />
0xA4-0xA5[12-0] PID_31, PID storage register 13 bits wide</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Astrometa_DVB-T2
Astrometa DVB-T2
2014-03-16T20:45:36Z
<p>Merbanan: RTL2832P configuration</p>
<hr />
<div>==RTL2832P configuration==<br />
<br />
The RTL2832P has 2 PID filter paths. One for the internal demod and one for a possible external one.<br />
<br />
=== External ts mode ===<br />
0x21[3] enable_ETS, set to enable external ts input<br />
0x21[5] pass_err, when set reject error packets<br />
0x21[6] PID_mode, when set reject matched PIDs<br />
0x21[7] PID_output, when set output data from enabled PID filters<br />
0x22[7-0] PID_enable, when set enable PID in corresponding register (0-7)<br />
0x23[7-0] PID_enable, when set enable PID in corresponding register (8-15)<br />
0x24[7-0] PID_enable, when set enable PID in corresponding register (16-23)<br />
0x25[7-0] PID_enable, when set enable PID in corresponding register (24-31)<br />
0x26-0x27[12-0] PID_0, PID storage register 13 bits wide<br />
0x28-0x29[12-0] PID_1, PID storage register 13 bits wide<br />
0x2A-0x2B[12-0] PID_2, PID storage register 13 bits wide<br />
0x2C-0x2D[12-0] PID_3, PID storage register 13 bits wide<br />
0x2E-0x2F[12-0] PID_4, PID storage register 13 bits wide<br />
0x30-0x31[12-0] PID_5, PID storage register 13 bits wide<br />
0x32-0x33[12-0] PID_6, PID storage register 13 bits wide<br />
0x34-0x35[12-0] PID_7, PID storage register 13 bits wide<br />
0x36-0x37[12-0] PID_8, PID storage register 13 bits wide<br />
0x38-0x39[12-0] PID_9, PID storage register 13 bits wide<br />
0x3A-0x3B[12-0] PID_10, PID storage register 13 bits wide<br />
0x3C-0x3D[12-0] PID_11, PID storage register 13 bits wide<br />
0x3E-0x3F[12-0] PID_12, PID storage register 13 bits wide<br />
0x40-0x41[12-0] PID_13, PID storage register 13 bits wide<br />
0x42-0x43[12-0] PID_14, PID storage register 13 bits wide<br />
0x44-0x45[12-0] PID_15, PID storage register 13 bits wide<br />
0x46-0x47[12-0] PID_16, PID storage register 13 bits wide<br />
0x48-0x49[12-0] PID_17, PID storage register 13 bits wide<br />
0x4A-0x4B[12-0] PID_18, PID storage register 13 bits wide<br />
0x4C-0x4D[12-0] PID_19, PID storage register 13 bits wide<br />
0x4E-0x4F[12-0] PID_20, PID storage register 13 bits wide<br />
0x50-0x51[12-0] PID_21, PID storage register 13 bits wide<br />
0x52-0x53[12-0] PID_22, PID storage register 13 bits wide<br />
0x54-0x55[12-0] PID_23, PID storage register 13 bits wide<br />
0x56-0x57[12-0] PID_24, PID storage register 13 bits wide<br />
0x58-0x59[12-0] PID_25, PID storage register 13 bits wide<br />
0x5A-0x5B[12-0] PID_26, PID storage register 13 bits wide<br />
0x5C-0x5D[12-0] PID_27, PID storage register 13 bits wide<br />
0x5E-0x5F[12-0] PID_28, PID storage register 13 bits wide<br />
<br />
These filters would overlap with the 0x61 address.<br />
<br />
0x60-0x61[12-0] PID_29, PID storage register 13 bits wide<br />
0x62-0x63[12-0] PID_30, PID storage register 13 bits wide<br />
0x64-0x65[12-0] PID_31, PID storage register 13 bits wide<br />
<br />
Most likely the the external PID filter path has less then 32 pid filters.</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-25T22:02:23Z
<p>Merbanan: add lock</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8 in T1 bank, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Lock ===<br />
<br />
==== DVB-T2 ====<br />
<br />
* Read register 0x92 in T2 bank.<br />
* If the low nibble in the result is >12 there is a lock<br />
<br />
==== DVB-T ====<br />
<br />
* Read register 0x7F in T1 bank.<br />
* If the low nibble in the result is >8 there is a lock<br />
<br />
==== DVB-C ====<br />
<br />
* Read register 0x84 in C1 bank.<br />
* If the low nibble in the result is >7 there is a lock<br />
<br />
When lock is detected it means what the demod has:<br />
Signal, Carrier, Viterbi, Sync and Lock.<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-24T11:45:56Z
<p>Merbanan: /* Setting Digital TV standard */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T 2<br />
DVB-T2 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-24T00:04:03Z
<p>Merbanan: /* Demod mcu */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
You can control the cpu by writing to the 0xf5 register:<br />
<br />
* write 0x03 to stop the cpu<br />
* write 0x00 to start the cpu<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-23T23:33:01Z
<p>Merbanan: </p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod mcu ===<br />
<br />
You can check if the firmware is running by reading register 0xf5.<br />
<br />
* If bit 0 is 0 it is running<br />
* If bit 0 is 1 it is not running<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-05T00:07:02Z
<p>Merbanan: /* Configure demod for signal reception */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
{T2,0x30,0x80},<br />
{T2,0x32,0x00},<br />
{T2,0xf8,0x9f},<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-04T22:32:37Z
<p>Merbanan: </p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T2 ===<br />
<br />
Begin with a per MHz setup.<br />
==== 5MHz ====<br />
<br />
{T2,0x10,0x3e},<br />
{T2,0x11,0x70},<br />
{T2,0x12,0x64},<br />
{T2,0x13,0xe5},<br />
{T2,0x14,0x99},<br />
{T2,0x15,0x9a},<br />
{T2,0x16,0x1b},<br />
{T2,0x17,0xa9},<br />
{T2,0x18,0x1b},<br />
{T2,0x19,0xa9},<br />
<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0xf6},<br />
{T1,0xcd,0x01},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x46},<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-04T22:27:56Z
<p>Merbanan: /* Configure demod for signal reception */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration to the demod:<br />
<br />
=== DVB-C ===<br />
<br />
{T2,0x10,0x3f},<br />
{T2,0x11,0x50},<br />
{T2,0x12,0x2c},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0b},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x17},<br />
{T1,0xd4,0x09},<br />
{T1,0xd6,0x48},<br />
<br />
=== DVB-T ===<br />
Begin with a per MHz setup.<br />
==== 6MHz ====<br />
<br />
{T2,0x10,0x2c},<br />
{T2,0x11,0x94},<br />
{T2,0x12,0xdb},<br />
{T2,0x13,0xbf},<br />
{T2,0x14,0x55},<br />
{T2,0x15,0x55},<br />
{T2,0x16,0x15},<br />
{T2,0x17,0x6b},<br />
{T2,0x18,0x15},<br />
{T2,0x19,0x6b},<br />
{T1,0x46,0x00},<br />
<br />
==== 7MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0xa4},<br />
{T2,0x14,0x00},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x0f},<br />
{T2,0x17,0x2c},<br />
{T2,0x18,0x0f},<br />
{T2,0x19,0x2c},<br />
{T1,0x46,0x10},<br />
<br />
==== 8MHz ====<br />
<br />
{T2,0x10,0x39},<br />
{T2,0x11,0x11},<br />
{T2,0x12,0xbc},<br />
{T2,0x13,0x8f},<br />
{T2,0x14,0x80},<br />
{T2,0x15,0x00},<br />
{T2,0x16,0x08},<br />
{T2,0x17,0xee},<br />
{T2,0x18,0x08},<br />
{T2,0x19,0xee},<br />
{T1,0x46,0x00},<br />
<br />
And end with a common configuration.<br />
<br />
{T1,0xae,0x00},<br />
{T1,0xb0,0x0a},<br />
{T1,0xb4,0x00},<br />
{T1,0xcd,0x1f},<br />
{T1,0xd4,0x0a},<br />
{T1,0xd6,0x48},<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-04T20:31:59Z
<p>Merbanan: </p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T1 bank<br />
** Write 0x03 to register 0xf5 in T1 bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T1 bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T1 bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T1 bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
== Configure demod for signal reception ==<br />
<br />
* Write 0x00 to register 0xFF in T2 bank<br />
* Write 0x66 to register 0x00 in T2 bank<br />
* Write 0x00 to register 0x01 in T2 bank<br />
* Write 0x02 to register 0x02 in T2 bank<br />
* Set the Digital TV Standard<br />
* Set the demod bandwidth<br />
<br />
And depending on the selected standard / bandwidth configuration write one of the following configuration tables to the demod:<br />
<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-04T19:58:17Z
<p>Merbanan: /* I2C Adressing */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2 (T2)<br />
0x30 (0x18) - DVB-T (T1)<br />
0x34 (0x1a) - DVB-C (C1)<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T bank<br />
** Write 0x03 to register 0xf5 in T bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-04T19:57:44Z
<p>Merbanan: /* Demod Initialization */ add init table</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2 T1 and C1) {bank,reg,value}<br />
<br />
{T2,0x00,0x66},{T2,0x01,0x00},{T2,0x02,0x01},{T2,0x03,0x03},<br />
{T2,0x04,0x00},{T2,0x05,0x00},{T2,0x06,0x00},{T2,0x07,0x00},<br />
{T2,0x08,0x00},{T2,0x09,0x00},{T2,0x0a,0x00},{T2,0x0b,0x00},<br />
{T2,0x0c,0x00},{T2,0x0d,0x00},{T2,0x0e,0x00},{T2,0x0f,0x00},<br />
{T2,0x10,0x3e},{T2,0x11,0x70},{T2,0x12,0x64},{T2,0x13,0x8f},<br />
{T2,0x14,0x80},{T2,0x15,0x00},{T2,0x16,0x08},{T2,0x17,0xee},<br />
{T2,0x18,0x08},{T2,0x19,0xee},{T2,0x1a,0x43},{T2,0x1b,0x00},<br />
{T2,0x1c,0x74},{T2,0x1d,0xe4},{T2,0x1e,0x26},{T2,0x1f,0x4f},<br />
{T2,0x20,0x72},{T2,0x21,0x22},{T2,0x22,0x22},{T2,0x23,0x01},<br />
{T2,0x24,0x00},{T2,0x25,0x12},{T2,0x26,0x00},{T2,0x27,0x00},<br />
{T2,0x28,0x80},{T2,0x29,0x0c},{T2,0x2a,0xf4},{T2,0x2b,0x03},<br />
{T2,0x2c,0x00},{T2,0x2d,0x20},{T2,0x2e,0x88},{T2,0x2f,0x00},<br />
{T2,0x30,0x80},{T2,0x31,0x80},{T2,0x32,0x00},{T2,0x33,0x00},<br />
{T2,0x34,0x00},{T2,0x35,0x00},{T2,0x36,0x00},{T2,0x37,0x00},<br />
{T2,0x38,0xca},{T2,0x39,0x03},{T2,0x3a,0x02},{T2,0x3b,0x55},<br />
{T2,0x3c,0xd7},{T2,0x3d,0x00},{T2,0x3e,0x00},{T2,0x3f,0x22},<br />
{T2,0x40,0x00},{T2,0x41,0x38},{T2,0x42,0x22},{T2,0x43,0x00},<br />
{T2,0x44,0x38},{T2,0x45,0xd3},{T2,0x46,0x10},{T2,0x47,0xb5},<br />
{T2,0x48,0xa1},{T2,0x49,0x00},{T2,0x4a,0xd3},{T2,0x4b,0x07},<br />
{T2,0x4c,0x64},{T2,0x4d,0x0d},{T2,0x4e,0x00},{T2,0x4f,0x05},<br />
{T2,0x50,0x00},{T2,0x51,0x55},{T2,0x52,0x20},{T2,0x53,0x00},<br />
{T2,0x54,0x24},{T2,0x55,0x64},{T2,0x56,0x44},{T2,0x57,0x33},<br />
{T2,0x58,0x1f},{T2,0x59,0x00},{T2,0x5a,0x5a},{T2,0x5b,0x03},<br />
{T2,0x5c,0xc0},{T2,0x5d,0x00},{T2,0x5e,0x00},{T2,0x5f,0x03},<br />
{T2,0x60,0x00},{T2,0x61,0x00},{T2,0x62,0x11},{T2,0x63,0x40},<br />
{T2,0x64,0x84},{T2,0x65,0x04},{T2,0x66,0x0c},{T2,0x67,0x00},<br />
{T2,0x68,0x08},{T2,0x69,0x00},{T2,0x6a,0x00},{T2,0x6b,0x12},<br />
{T2,0x6c,0x21},{T2,0x6d,0x10},{T2,0x6e,0x01},{T2,0x6f,0x00},<br />
{T2,0x70,0x00},{T2,0x71,0x00},{T2,0x72,0xe8},{T2,0x73,0x48},<br />
{T2,0x74,0x40},{T2,0x75,0x00},{T2,0x76,0x1d},{T2,0x77,0x19},<br />
{T2,0x78,0x1d},{T2,0x79,0x19},{T2,0x7a,0x66},{T2,0x7b,0x8c},<br />
{T2,0x7c,0x9f},{T2,0x7d,0x08},{T2,0x7e,0x00},{T2,0x7f,0x00},<br />
{T2,0x80,0x00},{T2,0x81,0x00},{T2,0x83,0x00},{T2,0x84,0x00},<br />
{T2,0x85,0x00},{T2,0x86,0x00},{T2,0x87,0x00},{T2,0x88,0x00},<br />
{T2,0x89,0x00},{T2,0x8a,0x20},{T2,0x8b,0x49},{T2,0x8c,0x00},<br />
{T2,0xc4,0x00},{T2,0xc5,0x00},{T2,0xc6,0x00},{T2,0xc7,0x87},<br />
{T2,0xc8,0x40},{T2,0xc9,0x30},{T2,0xca,0x06},{T2,0xcb,0x02},<br />
{T2,0xcc,0x00},{T2,0xcd,0x3b},{T2,0xce,0x00},{T2,0xcf,0x00},<br />
{T2,0xd0,0x00},{T2,0xd1,0x00},{T2,0xd2,0x00},{T2,0xd3,0x40},<br />
{T2,0xd4,0x00},{T2,0xd5,0xf0},{T2,0xd6,0x02},{T2,0xd7,0x02},<br />
{T2,0xd8,0x01},{T2,0xd9,0x00},{T2,0xda,0x00},{T2,0xdb,0x00},<br />
{T2,0xdc,0x00},{T2,0xdd,0x00},{T2,0xde,0x00},{T2,0xdf,0x00},<br />
{T2,0xe0,0x00},{T2,0xe1,0x00},{T2,0xe2,0x00},{T2,0xe3,0x00},<br />
{T2,0xe4,0x00},{T2,0xe5,0x00},{T2,0xe6,0x00},{T2,0xe7,0x00},<br />
{T2,0xe9,0x00},{T2,0xea,0x00},{T2,0xeb,0x00},{T2,0xec,0xd3},<br />
{T2,0xed,0x31},{T2,0xee,0x00},{T2,0xef,0x00},{T2,0xf0,0x00},<br />
{T2,0xf1,0x00},{T2,0xf2,0x00},{T2,0xf3,0x00},{T2,0xf4,0x00},<br />
{T2,0xf5,0x00},{T2,0xf6,0x00},{T2,0xf8,0x9f},{T2,0xf9,0xd4},<br />
{T2,0xfa,0x00},{T2,0xfb,0x03},{T2,0xfc,0x00},{T2,0xfd,0x00},<br />
{T2,0xfe,0x00},{T2,0xff,0x02},{T1,0x00,0xba},{T1,0x01,0x13},<br />
{T1,0x02,0x80},{T1,0x03,0xba},{T1,0x04,0x91},{T1,0x05,0x40},<br />
{T1,0x06,0xe7},{T1,0x07,0x26},{T1,0x08,0xff},{T1,0x09,0x1b},<br />
{T1,0x0a,0x09},{T1,0x0b,0x08},{T1,0x0c,0x04},{T1,0x0d,0x2d},<br />
{T1,0x0e,0x09},{T1,0x0f,0x00},{T1,0x10,0x10},{T1,0x11,0x1f},<br />
{T1,0x12,0x08},{T1,0x13,0x00},{T1,0x14,0x00},{T1,0x15,0x03},<br />
{T1,0x16,0x00},{T1,0x17,0x00},{T1,0x18,0x00},{T1,0x19,0xb0},<br />
{T1,0x1a,0x00},{T1,0x1b,0x00},{T1,0x1c,0x00},{T1,0x1d,0xe0},<br />
{T1,0x1e,0x6c},{T1,0x1f,0x33},{T1,0x20,0x4a},{T1,0x21,0x03},<br />
{T1,0x22,0x00},{T1,0x23,0x01},{T1,0x24,0x05},{T1,0x25,0x96},<br />
{T1,0x26,0x43},{T1,0x27,0x00},{T1,0x28,0x01},{T1,0x29,0x15},<br />
{T1,0x2a,0xa2},{T1,0x2b,0xc3},{T1,0x2c,0xf5},{T1,0x2d,0x22},<br />
{T1,0x2e,0x87},{T1,0x2f,0xd3},{T1,0x30,0x00},{T1,0x31,0x55},<br />
{T1,0x32,0x33},{T1,0x33,0x61},{T1,0x34,0x22},{T1,0x35,0x01},<br />
{T1,0x36,0x02},{T1,0x37,0x40},{T1,0x38,0x40},{T1,0x39,0x46},<br />
{T1,0x3a,0x25},{T1,0x3b,0x04},{T1,0x3c,0x00},{T1,0x3d,0x04},<br />
{T1,0x3e,0x00},{T1,0x3f,0x00},{T1,0x40,0x3b},{T1,0x41,0x20},<br />
{T1,0x42,0x00},{T1,0x43,0x3f},{T1,0x44,0x1f},{T1,0x45,0x05},<br />
{T1,0x46,0x00},{T1,0x47,0x00},{T1,0x48,0x05},{T1,0x49,0xf0},<br />
{T1,0x4a,0x00},{T1,0x4b,0x00},{T1,0x4c,0x1f},{T1,0x4d,0x0f},<br />
{T1,0x4e,0x39},{T1,0x4f,0x03},{T1,0x50,0xf8},{T1,0x51,0xf4},<br />
{T1,0x52,0x08},{T1,0x53,0xf8},{T1,0x54,0xea},{T1,0x55,0xf0},<br />
{T1,0x56,0x04},{T1,0x57,0x20},{T1,0x58,0x12},{T1,0x59,0x12},<br />
{T1,0x5a,0x02},{T1,0x5b,0x20},{T1,0x5c,0x1a},{T1,0x5d,0x08},<br />
{T1,0x5e,0xad},{T1,0x5f,0x33},{T1,0x60,0x95},{T1,0x61,0x8f},<br />
{T1,0x62,0x80},{T1,0x63,0x00},{T1,0x64,0x76},{T1,0x65,0x54},<br />
{T1,0x66,0x87},{T1,0x67,0x65},{T1,0x68,0x66},{T1,0x69,0x54},<br />
{T1,0x6a,0x4a},{T1,0x6b,0x86},{T1,0x6c,0x13},{T1,0x6d,0x31},<br />
{T1,0x6e,0x2d},{T1,0x6f,0x07},{T1,0x70,0x00},{T1,0x71,0x40},<br />
{T1,0x72,0x00},{T1,0x73,0x00},{T1,0x74,0x00},{T1,0x75,0x10},<br />
{T1,0x76,0x0c},{T1,0x77,0x0c},{T1,0x78,0x59},{T1,0x79,0x00},<br />
{T1,0x7a,0x00},{T1,0x7b,0x00},{T1,0x7c,0x00},{T1,0x7d,0x05},<br />
{T1,0x88,0x1e},{T1,0x89,0x49},{T1,0x8a,0x31},{T1,0x8b,0x1a},<br />
{T1,0x8c,0x2c},{T1,0x8d,0x3f},{T1,0x8e,0x7f},{T1,0x8f,0x07},<br />
{T1,0xa5,0x00},{T1,0xa6,0x00},{T1,0xa9,0x00},{T1,0xaa,0x00},<br />
{T1,0xab,0x00},{T1,0xae,0x00},{T1,0xaf,0x00},{T1,0xb0,0x0a},<br />
{T1,0xb1,0x7a},{T1,0xb2,0x40},{T1,0xb3,0x5c},{T1,0xb4,0xf6},<br />
{T1,0xb5,0x31},{T1,0xb6,0xc0},{T1,0xb7,0xff},{T1,0xb8,0x88},<br />
{T1,0xb9,0xff},{T1,0xba,0xaa},{T1,0xbb,0x00},{T1,0xbc,0x08},<br />
{T1,0xbd,0x03},{T1,0xbe,0x00},{T1,0xbf,0x00},{T1,0xc0,0xbf},<br />
{T1,0xc1,0x00},{T1,0xc2,0x00},{T1,0xc3,0xff},{T1,0xc4,0x20},<br />
{T1,0xc5,0x80},{T1,0xc6,0xff},{T1,0xc7,0xff},{T1,0xc8,0xff},<br />
{T1,0xc9,0xe0},{T1,0xca,0x80},{T1,0xcb,0x00},{T1,0xcc,0x00},<br />
{T1,0xcd,0x01},{T1,0xce,0x00},{T1,0xcf,0x54},{T1,0xd0,0x23},<br />
{T1,0xd1,0x47},{T1,0xd2,0x01},{T1,0xd3,0x00},{T1,0xd4,0x09},<br />
{T1,0xd5,0x47},{T1,0xd6,0x46},{T1,0xd7,0x00},{T1,0xd8,0x00},<br />
{T1,0xd9,0xe1},{T1,0xda,0x03},{T1,0xdb,0x08},{T1,0xdc,0xb8},<br />
{T1,0xdd,0x08},{T1,0xde,0x0c},{T1,0xdf,0x90},{T1,0xe6,0x00},<br />
{T1,0xe7,0x00},{T1,0xe8,0x00},{T1,0xec,0x00},{T1,0xed,0x00},<br />
{T1,0xee,0x00},{T2,0xfb,0x03},{T1,0xf0,0x00},{T1,0xf1,0x00},<br />
{T1,0xf2,0x00},{T1,0xf3,0x00},{T1,0xf4,0x00},{T1,0xf5,0x01},<br />
{T1,0xf7,0x00},{T1,0xf8,0x00},{T1,0xf9,0x07},{T1,0xfa,0xff},<br />
{T1,0xfb,0x00},{T1,0xfc,0x00},{T1,0xfd,0x30},{T1,0xfe,0x00},<br />
{T1,0xff,0x02},{C1,0x00,0xb0},{C1,0x01,0x00},{C1,0x02,0x11},<br />
{C1,0x03,0x18},{C1,0x04,0x04},{C1,0x05,0xe0},{C1,0x06,0x5f},<br />
{C1,0x07,0x27},{C1,0x08,0x30},{C1,0x09,0xff},{C1,0x0a,0xc0},<br />
{C1,0x0b,0xaa},{C1,0x0c,0xbb},{C1,0x0d,0xee},{C1,0x0e,0xaa},<br />
{C1,0x0f,0xaa},{C1,0x10,0x0d},{C1,0x11,0xab},{C1,0x12,0x0b},<br />
{C1,0x13,0x3c},{C1,0x14,0x18},{C1,0x15,0xd9},{C1,0x16,0x51},<br />
{C1,0x17,0xec},{C1,0x18,0x00},{C1,0x19,0xbe},{C1,0x1a,0xd6},<br />
{C1,0x1b,0x1c},{C1,0x1c,0x0b},{C1,0x1d,0x3c},{C1,0x1e,0x29},<br />
{C1,0x1f,0x00},{C1,0x20,0x00},{C1,0x21,0x00},{C1,0x22,0xa0},<br />
{C1,0x23,0x94},{C1,0x24,0xaf},{C1,0x25,0x01},{C1,0x26,0x00},<br />
{C1,0x27,0x00},{C1,0x28,0x00},{C1,0x29,0x00},{C1,0x2a,0x00},<br />
{C1,0x2b,0x00},{C1,0x2c,0x00},{C1,0x2d,0x00},{C1,0x2e,0x00},<br />
{C1,0x2f,0x0c},{C1,0x30,0x3b},{C1,0x31,0x41},{C1,0x32,0x0c},<br />
{C1,0x33,0x02},{C1,0x34,0xb1},{C1,0x35,0xed},{C1,0x36,0x60},<br />
{C1,0x37,0xcc},{C1,0x38,0x6c},{C1,0x39,0x7d},{C1,0x3a,0xb1},<br />
{C1,0x3b,0xed},{C1,0x3c,0x69},{C1,0x3d,0xb3},{C1,0x3e,0xed},<br />
{C1,0x3f,0x40},{C1,0x40,0xdb},{C1,0x41,0xda},{C1,0x42,0x79},<br />
{C1,0x43,0x87},{C1,0x44,0xbc},{C1,0x45,0x3f},{C1,0x46,0xb7},<br />
{C1,0x47,0x5e},{C1,0x48,0x1c},{C1,0x49,0xb7},{C1,0x4a,0x56},<br />
{C1,0x4b,0xb7},{C1,0x4c,0x56},{C1,0x4d,0xb7},{C1,0x4e,0x56},<br />
{C1,0x4f,0x63},{C1,0x50,0xd5},{C1,0x51,0x74},{C1,0x52,0x95},<br />
{C1,0x53,0x5f},{C1,0x54,0xc0},{C1,0x55,0x73},{C1,0x56,0x28},<br />
{C1,0x57,0xc4},{C1,0x58,0x69},{C1,0x59,0x55},{C1,0x5a,0x55},<br />
{C1,0x5b,0x40},{C1,0x5c,0x60},{C1,0x5d,0xfd},{C1,0x5e,0x00},<br />
{C1,0x5f,0x00},{C1,0x60,0x30},{C1,0x61,0x29},{C1,0x62,0x13},<br />
{C1,0x63,0xf0},{C1,0x64,0x00},{C1,0x65,0x96},{C1,0x66,0x72},<br />
{C1,0x67,0x1b},{C1,0x68,0x2d},{C1,0x69,0x97},{C1,0x6a,0x4b},<br />
{C1,0x6b,0xde},{C1,0x6c,0x88},{C1,0x6d,0x00},{C1,0x6e,0x00},<br />
{C1,0x6f,0x00},{C1,0x70,0xab},{C1,0x71,0x2b},{C1,0x72,0x10},<br />
{C1,0x73,0xf4},{C1,0x74,0x47},{C1,0x75,0x57},{C1,0x76,0x40},<br />
{C1,0x77,0xaa},{C1,0x78,0xaa},{C1,0x79,0x01},{C1,0x7a,0x00},<br />
{C1,0x7b,0x07},{C1,0x7c,0x50},{C1,0x80,0x00},{C1,0x81,0x88},<br />
{C1,0x82,0x00},{C1,0xf0,0x00},{C1,0xf1,0x5e},{C1,0xf2,0xec},<br />
{C1,0xf3,0x00},{C1,0xf4,0x5e},{C1,0xf5,0xec},{C1,0xf6,0x05},<br />
{T2,0xfb,0x03},{C1,0xfc,0x00},{C1,0xfd,0x00},{C1,0xfe,0x00},<br />
{C1,0xff,0x02},<br />
<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T bank<br />
** Write 0x03 to register 0xf5 in T bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-01T00:36:53Z
<p>Merbanan: Setting demod bandwidth</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T bank<br />
** Write 0x03 to register 0xf5 in T bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03 in T2 bank<br />
<br />
=== Setting demod bandwidth ===<br />
<br />
Select the value representing the bandwidth you want from the list.<br />
<br />
5MHz 3<br />
6MHz 2<br />
7MHz 1<br />
8MHz 0<br />
<br />
* Write the value to register 0x04 in T2 bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-11-01T00:34:41Z
<p>Merbanan: Setting Digital TV standard</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T bank<br />
** Write 0x03 to register 0xf5 in T bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
=== Setting Digital TV standard ===<br />
<br />
Select the value representing the standard you want from the list.<br />
<br />
DVB-T2 2<br />
DVB-T 3<br />
DVB-C 4<br />
<br />
* Write the value to register 0x03<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-10-31T20:53:32Z
<p>Merbanan: /* Demod Initialization */</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Write init reg values for all 3 register banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
** Write 0x20 to register 0xf0 in T bank<br />
** Write 0x03 to register 0xf5 in T bank (this most likely set the mcu to reset state)<br />
* Load firmware for demod<br />
** Write all firmware bytes to register 0xf6 to fill the mcu memory<br />
* Start demod firmware<br />
** Write 0x00 to register 0xf5 in T bank<br />
* Check parity<br />
** Read register 0xf8, if byte 5 (0x10) is set the parity check failed.<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-10-31T02:36:32Z
<p>Merbanan: better probe description</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Load init reg values for all 3 banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
* Load firmware for demod<br />
* Check parity<br />
<br />
=== Demod probe ===<br />
<br />
* Read register 0xFF in T2 bank<br />
<br />
The answer should be 0x02.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-10-31T02:35:16Z
<p>Merbanan: TS mode</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Load init reg values for all 3 banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
* Load firmware for demod<br />
* Check parity<br />
<br />
=== Demod probe ===<br />
<br />
The T2 demod bank have a register that can be used to id the chip. Doing a read on register 0xFF should return the answer 0x2.<br />
<br />
=== TS mode ===<br />
<br />
How to set chip ts mode.<br />
<br />
==== Parallel TS with fixed clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE1 to register 0xD9 in T bank<br />
<br />
==== Parallel TS with variable clock ====<br />
<br />
* Write 0x00 to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
==== Serial TS with variable clock ====<br />
<br />
* Write 0x1D to register 0x08 in T2 bank<br />
* Write 0xE3 to register 0xD9 in T bank<br />
<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-10-30T20:06:34Z
<p>Merbanan: Add demod probe documentation</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Load init reg values for all 3 banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
* Load firmware for demod<br />
* Check parity<br />
<br />
=== Demod probe ===<br />
<br />
The T2 demod bank have a register that can be used to id the chip. Doing a read on register 0xFF should return the answer 0x2.<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Panasonic_MN88472
Panasonic MN88472
2013-10-13T16:19:18Z
<p>Merbanan: Initial commit</p>
<hr />
<div>=== NM88472 ===<br />
<br />
The NM88472 is a [[DVB-T]]/[[DVB-T2]]/[[DVB-C]] [[demodulator]] chip manufactured by [[Panasonic]].<br />
<br />
=== I2C Adressing ===<br />
<br />
The chips has 3 I2C addresses, one for each demodulator bank:<br />
<br />
8 bit (7 bit)<br />
0x38 (0x1c) - DVB-T2<br />
0x30 (0x18) - DVB-T<br />
0x34 (0x1a) - DVB-C<br />
<br />
<br />
=== Demod Initialization === <br />
<br />
* Load init reg values for all 3 banks (T2/T and last C)<br />
* Prepare DVB-T bank for firmware upload<br />
* Load firmware for demod<br />
* Check parity<br />
<br />
[[Category:Demodulator]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-03-02T11:56:35Z
<p>Merbanan: /* calculate_parameters */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 5<br />
| VCOBAND<br />
| This controls the frequency operating range of the tuner. Low 4 bits can be 0 or 4, High 4 bits can be 1,3,5,7,9.<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in Hz.<br />
<br />
* call set_parameters with freq and command equal to tune<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and command equal to tune_next<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and command equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and command equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and command<br />
<br />
* call calculate_parameters with freq and command<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
==== calculate_parameters ====<br />
Not complete yet*<br />
<br />
arguments freq (in Hz) and command<br />
<br />
* if freq is less then 60000000 or greater then 900000000<br />
** return error<br />
<br />
* if command is equal to tune_next<br />
** write g_prev_command to cmd_tmp<br />
* else<br />
** write command to g_prev_command<br />
<br />
* write 36125000 to IF<br />
* write 1232000000 to X<br />
* write 920000000 to Y<br />
* write ((freq + X) divided by 4) plus 500000) to Z<br />
* write (1000000 * Z) divided by 1000000 to T1<br />
* write (4000000* Z) divided by 1000000 - Y - freq to T2<br />
* write (4000000* Z) divided by 1000000 - Y - freq - IF to T3<br />
* write T3 divided by 4000000 to T4<br />
* write T3 divided by 4 to T5<br />
* write T1 modulus 8000000 divided by 1000000 to T6<br />
* write (((T5 plus 15777216 multiplied by T4) multiplied by 16) plus 500000) divided by 1000000 to T7<br />
<br />
* write T4 to freq_slot5<br />
* write T7 truncated to 8 bits to freq_slot7<br />
* write 2 multiplied by (T7 shifted left 8) + 137 to freq_slot8<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-18T12:45:54Z
<p>Merbanan: /* Tuner set frequency */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 5<br />
| VCOBAND<br />
| This controls the frequency operating range of the tuner. Low 4 bits can be 0 or 4, High 4 bits can be 1,3,5,7,9.<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in Hz.<br />
<br />
* call set_parameters with freq and command equal to tune<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and command equal to tune_next<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and command equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and command equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and command<br />
<br />
* call calculate_parameters with freq and command<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
==== calculate_parameters ====<br />
Not complete yet*<br />
<br />
arguments freq (in Hz) and command<br />
<br />
* if freq is less then 60000000 or greater then 900000000<br />
** return error<br />
<br />
* if command is equal to tune_next<br />
** write g_prev_command to cmd_tmp<br />
* else<br />
** write command to g_prev_command<br />
<br />
* write 36125000 to IF<br />
* write 1232000000 to X<br />
* write 920000000 to Y<br />
* write ((freq + X) divided by 4) plus 500000) to Z<br />
* write (1000000 * Z) divided by 1000000 to T1<br />
* write (4000000* Z) divided by 1000000 - Y - freq to T2<br />
* write (4000000* Z) divided by 1000000 - Y - freq - IF to T3<br />
* write T3 divided by 4000000 to T4<br />
* write T3 divided by 4 to T5<br />
* write T1 modulus 8000000 divided by 1000000 to T6<br />
* write (((T5 plus 15777216 multiplied by T4) multiplied by 16) plus 500000) divided by 1000000 to T7<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-18T08:53:57Z
<p>Merbanan: /* Tuner Init */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 5<br />
| VCOBAND<br />
| This controls the frequency operating range of the tuner. Low 4 bits can be 0 or 4, High 4 bits can be 1,3,5,7,9.<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and command equal to tune<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and command equal to tune_next<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and command equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and command equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and command<br />
<br />
* call calculate_parameters with freq and command<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-18T07:52:58Z
<p>Merbanan: /* Tuner set frequency */ try_count -> command</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 5<br />
| VCOBAND<br />
| This controls the frequency operating range of the tuner. Low 4 bits can be 0 or 4, High 4 bits can be 1,3,5,7,9.<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and command equal to tune<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and command equal to tune_next<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and command equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and command equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and command<br />
<br />
* call calculate_parameters with freq and command<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if command is equal to tune_next<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-15T13:11:37Z
<p>Merbanan: /* Tuner registers */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 5<br />
| VCOBAND<br />
| This controls the frequency operating range of the tuner. Low 4 bits can be 0 or 4, High 4 bits can be 1,3,5,7,9.<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-15T10:25:09Z
<p>Merbanan: initial Tuner reg meanings</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Tuner registers==<br />
<br />
Indexed from 0.<br />
<br />
{| class="wikitable"<br />
|-<br />
! Index<br />
! Name<br />
! Description<br />
|-<br />
| 1<br />
| OP<br />
| 0x00 = start tuner with programmed registers, 0x80 = set tuner to programming mode<br />
|-<br />
| 17<br />
| LNA<br />
| 0xF0 = disable LNA hardware power, used for sleep(), 0xF9 and 0xFD used to enable hardware with LNA on/off<br />
|}<br />
<br />
==Description of how to program the chip==<br />
<br />
<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-13T13:55:32Z
<p>Merbanan: /* Description of how to program the chip */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17* (this can be 0x0D in some cases)<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-13T13:30:51Z
<p>Merbanan: /* set_tuner_off */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-13T13:29:42Z
<p>Merbanan: /* set_tuner_off */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical or 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-13T13:19:40Z
<p>Merbanan: /* set_tuner_off */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into tmp<br />
** write tmp logical and 0xF0 into tmp<br />
** write tmp to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2010-01-13T10:38:51Z
<p>Merbanan: QT1010 add tuner on / off, not complete though</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
<br />
<br />
===Tuner On/Off===<br />
This method has 1 argument, curr set to either 0 or 1<br />
<br />
==== set_tuner_off ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* if curr is 1<br />
** read tuner register 17 into reg17<br />
** write reg17 logical and 0xF0 into reg17<br />
** write reg17 to tuner register 17<br />
* write 0x7F to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical or 0xF into tmp<br />
* write tmp to tuner register 5<br />
* write 0xFF to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
<br />
==== set_tuner_on ====<br />
<br />
* write 0x80 to tuner register 1<br />
<br />
* write 0x00 to tuner register 2<br />
* read tuner register 5 into tmp<br />
* write tmp logical and 0xF0 into tmp<br />
* write tmp to tuner register 5<br />
* write 0x00 to tuner register 6<br />
<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-29T10:31:43Z
<p>Merbanan: /* Tuner Init */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices) LNA<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-28T20:39:02Z
<p>Merbanan: QT1010 set_parameters complete</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34<br />
* if reg34 is less equal to 0xFE<br />
** write reg34 plus 1 to tuner register 34<br />
* read tuner register 5 into reg5<br />
* read tuner register 34 into reg34<br />
* write 0xD0 to tuner register 35<br />
* write 0x00 to tuner register 30<br />
* write 0xE0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 35<br />
** if register 35 bit 6 is set<br />
*** break out of loop<br />
<br />
* read tuner register 35 into reg35<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 36<br />
* write 0x00 to tuner register 30<br />
* write 0xF0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 36<br />
** if register 36 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x7F to tuner register 20<br />
* write 0x7F to tuner register 21<br />
<br />
* if try_counter is equal to 1<br />
** if reg5 is less equalt to 0x74<br />
*** write reg5 minus 4 into reg5_3<br />
* write reg5_3 to tuner register 5<br />
* write 0x00 to tuner register 6<br />
* write 0x1F to tuner register 21<br />
* write 0xFF to tuner register 22<br />
* write 0xFF to tuner register 24<br />
<br />
* if reg31 is greater equal to 0x50<br />
** write 0x50 into reg31<br />
* if reg32 is greater equal to 0x12<br />
** write 0x12 into reg32<br />
<br />
* write reg31 plus freq_slot10 to tuner register 31<br />
* write reg32 plus freq_slot11 to tuner register 32<br />
* write reg33 to tuner register 33<br />
* write reg37 to tuner register 37<br />
* write reg38 to tuner register 38<br />
<br />
* write 0x96 to tuner register 0<br />
* write 0x00 to tuner register 2<br />
* write 0x00 to tuner register 1<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-28T19:52:41Z
<p>Merbanan: /* set_parameters */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
* write 0x91 to tuner register 18*<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
<br />
* if reg5_1 is equal to 0x34<br />
** if freq_slot12 is larger equal to 0xF0<br />
*** if freq_slot12 is less equal to 0xFA<br />
**** write freq_slot12 minus 0x20 into freq_slot12<br />
*** else<br />
**** write 0xDA into freq_slot12<br />
** else<br />
*** write 0xD0 into freq_slot12<br />
** write freq_slot12 into tmp_var1<br />
* else<br />
** write 0xD0 into tmp_var1<br />
<br />
* write tmp_var1 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-28T17:47:04Z
<p>Merbanan: /* set_parameters */</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 26<br />
* write 0x00 to tuner register 27<br />
* write freq_slot8 to tuner register 28<br />
* write 0xFD to tuner register 17*<br />
<br />
<br />
<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-28T12:52:48Z
<p>Merbanan: alternative value</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14* (or 0xB7 might work better on some older devices)<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 10<br />
* write 0x00 to tuner register 11<br />
* write freq_slot8 to tuner register 12<br />
<br />
<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-27T18:51:38Z
<p>Merbanan: one forth of QT1010 set_parameters method</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14*<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
==== set_parameters ====<br />
arguments freq and try_count<br />
<br />
* call calculate_parameters with freq and try_count<br />
* write 0x80 to tuner register 1<br />
* write 0x3F to tuner register 2<br />
<br />
* if try_count is equal to 1<br />
** if reg5 is less then 0x74<br />
*** set reg5_1 to reg_5 plus 0x20<br />
<br />
* write reg5_1 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write freq_slot2 to tuner register 7<br />
* write freq_slot1 to tuner register 8<br />
* write freq_slot4 to tuner register 9<br />
* write freq_slot5 to tuner register 10<br />
* write freq_slot6 to tuner register 11<br />
* write 0xE1 to tuner register 12<br />
* write freq_slot7 to tuner register 10<br />
* write 0x00 to tuner register 11<br />
* write freq_slot8 to tuner register 12<br />
<br />
<br />
[[Category:Tuners]]</div>
Merbanan
http://www.linuxtv.org/wiki/index.php/Quantek_QT1010
Quantek QT1010
2009-12-27T18:33:54Z
<p>Merbanan: Added one of the set methods</p>
<hr />
<div>The Quantek QT1010 is a wideband [[Tuners: Supported Tuners|tuner]] chip.<br />
==Features==<br />
*48MHz-860MHz frequency range (bands I, II, III, IV).<br />
*30MHz-60MHz IF output range.<br />
*NTSC, PAL, SECAM broadcast formats.<br />
*[[DVB-C]], [[DVB-T]], [[ATSC]] and [[ISDB-T]] support.<br />
<br />
==External Links==<br />
[http://www.quantek-inc.com/qt1010.html QT1010 Product page at qantek-inc.com]<br />
<br />
==Description of how to program the chip==<br />
<br />
===Tuner context===<br />
<br />
The tuner has a global context for some variables. They can be used anytime in the init and set methods.<br />
<br />
* reg31<br />
* reg32<br />
* reg34<br />
* reg34_1<br />
* reg34_2<br />
* reg34_3<br />
* reg34_4<br />
* reg34_5<br />
* reg34_6<br />
* reg34_7<br />
* reg34_8<br />
* reg37<br />
* reg38<br />
<br />
===Tuner Init===<br />
This method has no arguments.<br />
<br />
<br />
* write 0x80 to tuner register 1<br />
* write 0x84 to tuner register 13<br />
* write 0xB4 to tuner register 14*<br />
* write 0x23 to tuner register 42<br />
* write 0xDC to tuner register 44<br />
* write 0x40 to tuner register 37<br />
* write 0x00 to tuner register 30<br />
* write 0x81 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 37 into reg37<br />
** if reg37 bit 8 is set<br />
*** break out of loop<br />
<br />
* read tuner register 37 into reg37<br />
* write 0x00 to tuner register 30<br />
* write 0x23 to tuner register 42<br />
* write 0x70 to tuner register 43<br />
* write 0x08 to tuner register 38<br />
* write 0x00 to tuner register 30<br />
* write 0x82 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 38 into reg38<br />
** if reg38 bit 5 is set<br />
*** break out of loop<br />
<br />
* read tuner register 38 into reg38<br />
* write 0x00 to tuner register 30<br />
* write 0x14 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x28 to tuner register 7<br />
* write 0x0B to tuner register 8<br />
* write 0xFD to tuner register 17*<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x80 to tuner register 1<br />
* write 0x0D to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* write 0x40 to tuner register 6<br />
* write 0xF0 to tuner register 22<br />
* write 0x38 to tuner register 2<br />
* write 0x19 to tuner register 3<br />
* write 0x20 to tuner register 31<br />
* write 0xE0 to tuner register 32<br />
* write 0x00 to tuner register 30<br />
* write 0x84 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 31 into reg31<br />
** if register 31 bit 7 is set<br />
*** break out of loop<br />
<br />
* read tuner register 31 into reg31<br />
* read tuner register 32 into reg32<br />
* write 0x00 to tuner register 30<br />
* write 0x3F to tuner register 2<br />
* write 0x53 to tuner register 33<br />
* read tuner register 33 into reg33<br />
* write 0xFD to tuner register 17*<br />
* write 0x34 to tuner register 5<br />
* write 0x44 to tuner register 6<br />
* write 0x31 to tuner register 7<br />
* write 0x08 to tuner register 8<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_1<br />
* write 0x32 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_2<br />
* write 0x33 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_3<br />
* write 0x34 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_4<br />
* write 0x35 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_5<br />
* write 0x36 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_6<br />
* write 0x37 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_7<br />
* write 0x38 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0x00 to tuner register 30<br />
* read tuner register 34 into reg34_8<br />
* write 0x39 to tuner register 7<br />
* write 0xD0 to tuner register 34<br />
* write 0x00 to tuner register 30<br />
* write 0xD0 to tuner register 30<br />
<br />
* loop 30 times<br />
** read tuner register 34<br />
** if register 34 bit 6 is set<br />
*** break out of loop<br />
<br />
* write 0xD0 to tuner register 30<br />
* read tuner register 34 into reg34<br />
<br />
=== Tuner set frequency ===<br />
<br />
The frequency set method has one sub-method and one subsub-method.<br />
<br />
==== set_frequency ====<br />
<br />
This method has the frequency argument, called freq and in kHz.<br />
<br />
* call set_parameters with freq and try_count equal to 0<br />
* if reg35 equal to 0xE0<br />
** call set_parameters with freq and try_count equal to 2<br />
* if reg35 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 3<br />
* if reg34 equal to 0xFF<br />
** call set_parameters with freq and try_count equal to 1<br />
<br />
<br />
[[Category:Tuners]]</div>
Merbanan