Astrometa DVB-T2

RTL2832P configuration

The RTL2832P has 2 PID filter paths. One for the internal demod and one for a possible external one.

External ts mode

0x21[3]         enable_ETS, set to enable external ts input
0x21[5]         pass_err, when set reject error packets
0x21[6]         PID_mode, when set reject matched PIDs
0x21[7]         PID_output, when set output data from enabled PID filters
0x22[7-0]       PID_enable, when set enable PID in corresponding register (0-7)
0x23[7-0]       PID_enable, when set enable PID in corresponding register (8-15)
0x24[7-0]       PID_enable, when set enable PID in corresponding register (16-23)
0x25[7-0]       PID_enable, when set enable PID in corresponding register (24-31)
0x26-0x27[12-0] PID_0, PID storage register 13 bits wide
0x28-0x29[12-0] PID_1, PID storage register 13 bits wide
0x2A-0x2B[12-0] PID_2, PID storage register 13 bits wide
0x2C-0x2D[12-0] PID_3, PID storage register 13 bits wide
0x2E-0x2F[12-0] PID_4, PID storage register 13 bits wide
0x30-0x31[12-0] PID_5, PID storage register 13 bits wide
0x32-0x33[12-0] PID_6, PID storage register 13 bits wide
0x34-0x35[12-0] PID_7, PID storage register 13 bits wide
0x36-0x37[12-0] PID_8, PID storage register 13 bits wide
0x38-0x39[12-0] PID_9, PID storage register 13 bits wide
0x3A-0x3B[12-0] PID_10, PID storage register 13 bits wide
0x3C-0x3D[12-0] PID_11, PID storage register 13 bits wide
0x3E-0x3F[12-0] PID_12, PID storage register 13 bits wide
0x40-0x41[12-0] PID_13, PID storage register 13 bits wide
0x42-0x43[12-0] PID_14, PID storage register 13 bits wide
0x44-0x45[12-0] PID_15, PID storage register 13 bits wide
0x46-0x47[12-0] PID_16, PID storage register 13 bits wide
0x48-0x49[12-0] PID_17, PID storage register 13 bits wide
0x4A-0x4B[12-0] PID_18, PID storage register 13 bits wide
0x4C-0x4D[12-0] PID_19, PID storage register 13 bits wide
0x4E-0x4F[12-0] PID_20, PID storage register 13 bits wide
0x50-0x51[12-0] PID_21, PID storage register 13 bits wide
0x52-0x53[12-0] PID_22, PID storage register 13 bits wide
0x54-0x55[12-0] PID_23, PID storage register 13 bits wide
0x56-0x57[12-0] PID_24, PID storage register 13 bits wide
0x58-0x59[12-0] PID_25, PID storage register 13 bits wide
0x5A-0x5B[12-0] PID_26, PID storage register 13 bits wide
0x5C-0x5D[12-0] PID_27, PID storage register 13 bits wide
0x5E-0x5F[12-0] PID_28, PID storage register 13 bits wide

These filters would overlap with the 0x61 address.

0x60-0x61[12-0] PID_29, PID storage register 13 bits wide
0x62-0x63[12-0] PID_30, PID storage register 13 bits wide
0x64-0x65[12-0] PID_31, PID storage register 13 bits wide

Most likely the the external PID filter path has less then 32 pid filters.