[linux-dvb] Re: Tuning problems with the refactored drivers

["Robert Schlabbach" <robert_s@gmx.net>]

From: "Holger Waechtler" <holger@qanu.de>
> the problem is that some demods (and even some more sophisticated PLLs)
> require delays between writing two particular registers (usually in
> order to wait until new clocks, a new loop gain, whatever... settles
> down and the circuitry works stable again), don't know if it makes much
> sense to build an infrastructure for this -- sometimes these delays have
> even to be placed just inbetween consecutive register writes/reads. But
> I have to admit that I don't remember for sure if the ves1820/tda10021
> required it before or after the clearbit write...

The VES1820 does _not_ require any delays between register writes, at least
according to my observations. It only has one flaw: The AFC logic can
sometimes get "stuck", and requires a reset. This seems to happen when the
tuner PLL is changing the frequency, so you need to reset the VES1820 after
the tuner PLL has setlled to a new frequency. That's where the delay is
needed.

An even better solution might be a "watchdog" which reads the VES1820
status and VAFC registers, and if the status shows the demodulator is not
locked, and the VAFC value is outside a certain range (e.g. < -4 or > +4),
resets the chip.

I don't know if this bug still applies to the VES1820X or the TDA10021. I
sure hope Philips fixed it at some point...

Regards,
--
Robert Schlabbach
e-mail: robert_s@gmx.net
Berlin, Germany