[vdr] [VGA sync field] question to fb-radeon-intel.patch
vdr at toh.cx
Thu Mar 12 18:31:47 CET 2009
On Wed, Mar 11, 2009 at 06:15:04PM +0100, Paul Menzel wrote:
> 1. In your patchset the patch fb-radeon-intel.patch  does include
> changes to drivers/video/intelfb/intelfbhw.c although in the install
> instructions  it is stated that intel drivers do not need to be
sorry, install instructions are not up to date for the Intel version
of the patch.
> The changelog in 0.11 includes these two items.
> - patch against intelfb (kernel 2.6.26) to allow for PAL/SCART
> video timings. You now can use a regular SCART CRT as display
> for linux console.
> - fixed a bug in intelfb initialization which sporadically
> setup video timing with weirdous values
> I guess the installation instructions need to be updated for release
right. as said installation instructions have not been touched since
a while. I just included the plain Intel patches into the package.
There was not yet too much interest in the patches anyway. So I
did not want to waste my time for documentation:-)
> If this is correct I would update the instructions.
thank you for that.
> a) Why is MIN_CLOCK set to 25000 in intelfbhw.h ? What would be the
> downside of setting it to 10000?
MIN_CLOCK is set to 12000 by the patch. What allows for SCART suitable
dotclocks. I don't know why the original driver denies such low
> b) Where do I get information about the registers, like what DPLL_A and
> DPLL_VCO_ENABLE is? In the header file some values are assigned to them,
> but where is it documented what they mean?
DPLL_A (DPLLA_CTRL-DPLL A Control Register) is documented here:
Intel® 965 Express Chipset Family, Volume Three
Section: Display Clock Control Registers
The doc can be found here:
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