[linux-dvb] Re[2]: DVB-C it got worse!

[Micael Beronius <micael.beronius@telia.com>]

HW> Hmm, here were two explicit parentheses missing, I added them. Please
HW> update your sources and tell me if it works now...

OK, I have found the main problem (apart from the missing
parenthesis). The last reset command sequence does not set CLB bit to
one after soft reset.

It should be
  ves1820_writereg (fe, 0x00, reg0 | 0x01 );
                                   ^^^^^^

But I do not really think that there is a need to reset the chip up to
two times each call to ves1820_setup_reg0(). I would like to take, at
least, the last reset calls out.

I also for now have made the function to use auto inversion only if so
specified, since I feel it may work a bit better, but I'll test things
a bit more, primarily I will use the last cvs with the above patch to
see if I feel it is good enough. My gut feeling says that it is not as
good as the manual inversion setting when the zig-zag tuning starts,
which by the way always happen to me if I stay at the "correct"
frequency ( 322000000 for example always zigzags down to something
like 321625000 ).

By the way, I have also seen that I always get 2 outcommand error 1 when the
Convergence copyright are scrolling down, it seams that the arm is busy with
this little (unnecessary) scroll.



This is what I use now, for reference:

int ves1820_setup_reg0 (struct dvb_frontend *fe, u8 reg0, fe_spectral_inversion_t inversion)
{
    int autoinv = 0;

    reg0 |= GET_REG0(fe->data) & 0x42;   // Start without inversion

    switch (inversion) {
    case INVERSION_OFF:      /* XXX FIXME: reversed?? p. 25  Yes, this is reversed! /MBe */
        reg0 |= 0x20;
        break;
    case INVERSION_ON:
        break;
    case INVERSION_AUTO:
        autoinv++;
        break;
    }
    ves1820_writereg (fe, 0x00, reg0 & 0xfe);  // enter reset
    ves1820_writereg (fe, 0x00, reg0 | 0x01);  // leave reset

        /**
         *  check lock and toggle inversion bit if required...
         */
    if ( autoinv )  {
        if (!(ves1820_readreg (fe, 0x11) & 0x08)) {  // Locked?
            ddelay(1);
            if (!(ves1820_readreg (fe, 0x11) & 0x08)) {  // Locked?
                reg0 ^= 0x20;
                dprintk ("ves1820_setup_reg0: Setting Inversion bit to %d\n", (1 == (reg0 & 0x20)) );
                ves1820_writereg (fe, 0x00, reg0 | 0x01 );
            }
        }
    }
    SET_REG0(fe->data, reg0);
    return 0;
}



  Micael



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